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vsa.extc@coep.ac.in

Faculty

Dr. Vanita Agarwal

Assistant Professor

Senior Member IEEE, LMIEI

 

IRINS Profile - https://vidwan.inflibnet.ac.in/profile/68619

LinkedIn Profile - https://www.linkedin.com/in/vanita-agarwal-ba1ab3a5/

Google Scholar Profile - https://scholar.google.co.in/citations?hl=en&user=6zeCjn0AAAAJ

Publons Profile - https://publons.com/researcher/3027130/vanita-agarwal/

Scopus Profile - https://www.scopus.com/authid/detail.uri?authorId=57204101759

Designation: 

Assistant Professor

Email: 

vsa.extc@coep.ac.in
vsa.extc@coeptech.ac.in
vanita.iitb@gmail.com

Phone Number: 

02025507503

Date of Joining COEP: 

14/01/2011

Teaching Experience: 

12

Research Experience: 

4

Qualifications: 

  • PhD, Savitribai Phule Pune University (SPPU), July 2020 – Topic “Developing Instruction Set Architecture with Specific reference for IoT Application with support of Rough Set Techniques” under the guidance of Prof. R.A. Patil and Late Prof. A. B. Patki.
  • MTech, Microelectronics and VLSI Design, Indian Institute of Technology Bombay, India, 2010 – Topic “Unit Process Development for the Fabrication of Small Channel Length Transistors” under the guidance of Prof. Anil Kottantharayil.
  • B.E., Electronics & Telecommunication , Biju Pattnaik Technical University, Orissa, 2004

 

Workshops/FDP/Conferences/Lecture Series Organized:

  • TEQIP-II sponsored FDP on “Analog VLSI Design using Cadence tool”, December 10-14, 2014 by E&TC Department, COEP and Entuple Technologies. Course Co-ordinators: Mrs Vaishali Ingale, Vanita Agarwal, Shatrughan Ransubhe.
  • Industry Academia relationship enhancement for VLSI under IET Pune chapter on 20th, 21st and 30th January 2012 for Post graduate students.
    • Topics covered:
      • Power Semiconductor Devices by Fairchild Semiconductor India.
      • Storage Technologies and Networking by LSI Pune.
      • Timing Analysis in Digital Circuits by NI2 Designs.
      • Functional verification techniques by LSI Pune.
      • Physical design flow by LSI Pune.
  • Workshop on "Processor Design using Cadence Tensilica Processor Platform", during June 6 - 8, 2018 by E&TC Department, COEP  and Cadence Design Systems. Course Co-ordinator: Ms Vanita Agarwal, Dr. Vaishali Ingale, Mr. Sarang Shelke.

 

Certifications:

  1. System Verilog for Verification Part 1: Fundamentals (11/2022) by Kumar Khandagale  (Udemy)
  2. System Verilog for Verification Part 2: Projects (01/2023) by Kumar Khandagale  (Udemy)
  3. System Design Methodologies for Embedded, IoT, AI and HPC with Intel FPGA (05/2021) by EICT Academy IIT Guwahati
  4. RISC V Implementation Flow: RTL to GDS (04/2021) by EICT Academy IIT Guwahati
  5. Advanced VLSI Design - Low Power Electronics and Design (09/2014) by Kaushik Roy - Purdue University

 

Research Interest:

  • Processor Design - ISA Design, RTL Design and Verification using Verilog and System Verilog
  • Artificial Intelligence – Rough Set Theory, Fuzzy Set Theory, Chaos Theory
  • Hardware Security - Digital Circuit Design, Analog circuit design
  • Semiconductor Devices - Fabrication and Characterization

 

Outreach:

  • Worked as an External Expert on Interview Committee for Project Engineer selection at CDAC Bengaluru (2017 – 2019).
  • External Examiner for MTech Dissertation examination at SGGS Nanded (2019).
  • Delivered Expert lectures to SY BTech students of ECE, MTU Imphal on “Electronic Devices and Circuits” (2020).

 

Previous Work Experience:

Research Assistant, Nano-electronics Center, CEN, IITB – May 2006 to Dec 2010.

  • Worked in the project titled “RF Oscillator with On chip LC-Oscillator and sub-100nm transistors” under the guidance of Prof. V Ramgopal Rao which was a joint deliverable project between IIT Bombay and IISC Bangalore. It covered detailed in-hand device fabrication experience for integration of sub 500nm NMOS Transistor on Silicon.
  • Targeted on Optimization and Integration of PolySi, SiN, SiO2 films for fabrication of Sub 500nm channel NMOS Transistor using various processes like Oxidation, Deposition, Lithography and Etching.
  • Handling of CVD system and Dry Etching systems, SEM/EBL, Diffusion furnace, Ellipsometer, etc.

Teaching Responsibility: 

  • Teach Theory and Lab courses for Undergraduate and Post graduate: Electronic Devices and Circuits, Digital System Design, Digital CMOS VLSI Design, Configurable Logic Design and Verification, RTL Simulation and Synthesis with PLDs, Analog CMOS VLSI Design using innovative teaching and learning methodologies.
  • Framed problem statements and architected the solution for more than 10+ teams of B.Tech and 30+ M.Tech students during their final year project.

Additional Responsibility: 

  • Lab In-charge for VLSI Design lab (2014 – till date). Involved in setting up of VLSI design lab at COEP.
  • PG Coordinator for MTech (VLSI & ES) Programme (Aug 2019 – May 2023)
  • Faculty Advisor for BTech Electronics &Telecommunication (2014 - 2019).
  • Faculty Advisor – Astronomy Club, COEP.
  • Member - Postgraduate Syllabus design committee for VLSI and ES specialization     @AICTE, COEP.
  • Member - NSS (National Social service) activities since 2011 till date.
  • Member - Preparation of UGNBA and PGNBA SAR preparation 2015-16, 2022-23.
  • Member - Departmental representative for AICTE report preparation 2011-2012.
  • Member - FYBTech Admission committee.

Publications: 

No. of International Journal Publication – 08 (01 SCI Indexed, 02 Scopus Indexed)

No. of National Journal Publication - 01

No. of International Conference Publication – 19 (18 Scopus Indexed)

No. of National Conference Publication – 03

h-index:4, i10-index:2

 

International Journals

  1. Vanita Agarwal, R. A. Patil, A. B. Patki, “Architectural Considerations for Next generation IoT Processors", IEEE Systems Journal, Vol.13, No. 3, 2906-2917,ISSN:1937-9234c 2018 IEEE) https://ieeexplore.ieee.org/document/8611387
  2. Patil, N., Agarwal, V., "Performance Simulation of a Traffic Sign Recognition based Neural Network on Cadence’s Tensilica Vision P6 DSP using Xtensa Xplorer IDE”, WSEAS Transactions on Computer Research,  2022, 10, pp. 35–42 https://wseas.com/journals/cr/2022/a105118-004(2022).pdf 
  3. Vanita Agarwal, “Design And Implementation Of Similarity Detector Using Hashing On FPGA For Low End IoT Devices”, International Journal of Creative Research Thoughts (IJCRT), Volume 11, Issue 5 May 2023, ISSN: 2320-2882. https://www.ijcrt.org/viewfull.php?&p_id=IJCRT2305717
  4. Vartul Sharma, Vanita Agarwal, “Design of Capacitor less LDO Regulator by using cascode compensation technique”, International Research Journal of Engineering and Technology (IRJET), Volume: 05 Issue: 06, June 2018. https://www.irjet.net/archives/V5/i6/IRJET-V5I6322.pdf
  5. Sushil Shingade, Vanita Agarwal, “Design of Charge Pump for PLL with Reduction in Current Mismatch and Variation having Improved Voltage Swing”, International Research Journal of Engineering and Technology (IRJET), Volume: 05 Issue: 06, June 2018.  https://www.irjet.net/archives/V5/i6/IRJET-V5I6510.pdf
  6. Ashish Jadhao, Vanita Agarwal, “Design of an Efficient Hardware Searching algorithm”, International Research Journal of Engineering and Technology (IRJET), Volume: 05 Issue: 05, May 2018
  7. Nilesh Sharad Khandekar, Vanita Agarwal, “Timing Closure And Leakage Optimization Using MCMM Optimization”, International Journal of Industrial Electronics and Electrical Engineering, ISSN: 2347-6982, Volume-4, Issue-8, Aug.-2016
  8. Reshma B Chougale, Vanita Agarwal, “Design of suitable Magnitude Comparator Architecture for Big Data Analytics”, International Journal on Recent and Innovation Trends in Computing and Communication, 2017,  ISSN: 2321-8169, Volume: 5 Issue: 7.

 

National Journal

  1. Vanita Agarwal, Ashok Saraf, R A Patil, “Design Security and Reconfigurable VLSI designs for strategic IP development”, DEFCOM INDIA, Vol.2, No.1, Nov 2015, ISSN 2394-2398

 

International Conferences

  1. Shiwani Hukare, Vibha Vyas, Vanita Agarwal, “Design and Simulation of Physical Layer of Peripheral Component Interconnect Express (PCIe) Protocol”, 4th International Conference of Emerging Technology (INCET 2023), 26th to 28th May 2023
  2. S. K. Varma, C. Dhole, V. Vyas and V. Agarwal, "Implementation of Reduct and Core features of Rough Set Theory on FPGA," 2022 International Conference on Signal and Information Processing (IConSIP), Pune, India, 2022, pp. 1-5, doi: 10.1109/ICoNSIP49665.2022.10007441
  3. S. S. Waghmare, V. Agarwal and V. Kulkarni, "Design and Simulation of GPS(1.56-1.61GHz) RF Lattice and Ladder Type SAW Filter," 2022 International Conference on Industry 4.0 Technology (I4Tech), 2022, pp. 1-6, doi: 10.1109/I4Tech55392.2022.9952639
  4. A. Deshmukh, V. Agarwal and V. Ingale, "Study of Energy and Power Consumption of Rough Set Theory unit on FPGA," 2022 International Conference on Industry 4.0 Technology (I4Tech), 2022, pp. 1-6, doi: 10.1109/I4Tech55392.2022.9952700.
  5. A. R. Devaskar, V. Agarwal and V. Kulkarni, "Design and Simulation of Band 40 RF SAW Ladder-Type Filter," 2022 IEEE International Conference on Semiconductor Electronics (ICSE), 2022, pp. 53-56, doi: 10.1109/ICSE56004.2022.9863187 https://ieeexplore.ieee.org/document/9863187
  6. J. Wani, T. K. Allamsetty, R. Gherde and V. Agarwal, "HLS Implementation of Quantum Shor’s Algorithm Using Matrix Pruning" 2022 Second International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT), 2022, pp. 1-4, doi: 10.1109/ICAECT54875.2022.9807860 https://ieeexplore.ieee.org/document/9807860
  7. Saurabh Pandurang Bhosale, Dr. Vanita Agarwal, “Implementation of Special Load and Store Instruction for the RST Unit”, in proceedings of Scopus indexed 8th International Conference on Signal Processing and Integrated Networks (SPIN 2021), Noida, 26-27 August 2021. https://ieeexplore.ieee.org/document/9565995
  8. Shubham Tonde, Dr. Vanita Agarwal, “Implementation of Lower and Upper Approximation features of rough set theory on FPGA”, in proceedings of Scopus indexed 12th International Conference on Computing, Communication and Networking Technologies (ICCCNT 2021), Kharagpur, 6-8 July 2021. https://ieeexplore.ieee.org/abstract/document/9579822
  9. Prajakta Yeola, Prachi Kakani, Tanvi Kale, Vanita Agarwal, “Implementation of an Agent based model for Shortest path finding using Fractal decomposition in AI”, in proceedings of Scopus indexed International Conference on Communication, Information and Computing Technology ICCICT 2021, Mumbai, 25-27 June 2021. https://ieeexplore.ieee.org/document/9509935
  10. Shubhangee Kishan Varma, Dr. Vanita Agarwal, Dr. Ashok Chandak, “Implementation of rule-based testing for digital circuits using inductive logic programming”, in proceedings of Scopus indexed 5th International Conference on Inventive Communication and Computational Technologies(ICICCT2021), Tamil Nadu, 25-26 June2021. https://link.springer.com/chapter/10.1007/978-981-16-5529-6_10
  11. Anirudh Ingole, Vanita Agarwal, “Instruction Set Design for Elementary Set in Tensilica Xtensa", in proceedings of Scopus indexed 10th IEEE International Conference ICCCNT 2019, Kanpur, 6-7 July 2019. https://ieeexplore.ieee.org/document/8944687
  12. Viraj Khatri, Vanita Agarwal, “Modified MD5 Algorithm for Low end IoT edge Devices”, in proceedings of 10th International Conference on Communication, Computing and Networking ICCCNT 2019, 6-7 July 2019, Kanpur, INDIA. https://ieeexplore.ieee.org/document/8944533
  13. Agarwal V., Patil R.A., Adwani J., “Code Profiling for Rough Set Theory on DSP and Embedded Processors", In: Kolhe M., Tiwari S., Trivedi M., Mishra K. (eds), Advances in Data and Information Sciences. Lecture Notes in Networks and Systems, vol 94. Springer, Singapore. https://link.springer.com/chapter/10.1007/978-981-15-0694-9_28
  14. Agarwal V., Patil R.A., “Standard Library Tool Set for Rough Set Theory on FPGA", In: Kolhe M., Tiwari S., Trivedi M., Mishra K. (eds), Advances in Data and Information Sciences. Lecture Notes in Networks and Systems, vol 94. Springer, Singapore. https://link.springer.com/chapter/10.1007/978-981-15-0694-9_23
  15. Anjali Surkar and Vanita Agarwal, “Delay and Power Analysis of Current and Voltage Sense Amplifiers for SRAM at 180nm Technology ”,in proceeding of Scopus indexed International Conference on Electronics Communication and Aerospace Technology [ICECA 2019] held during 12 June 2019, at RVS Technical campus Coimbatore, Tamil Nadu, India. https://ieeexplore.ieee.org/document/8822122
  16. Ranjit Kolhal and Vanita Agarwal, “A Power and Static Noise Margin Analysis of different SRAM cells at 180nm Technology”, in proceeding of scopus indexed 3rd International Conference on Electronics Communication and Aerospace Technology [ICECA 2019] held during 12-14 june 2019, at RVS Technical campus Coimbatore, Tamil nadu,India. https://ieeexplore.ieee.org/document/8821868
  17. Nikhil Narsale and Vanita Agarwal, “Implementation of LEM2 Algorithm on FPGA”,in proceeding of scopus indexed 3rd International Conference on Electronics Communication and Aerospace Technology [ICECA 2019] held during 12-14 june 2019, at RVS Technical campus Coimbatore, Tamil nadu,India. https://ieeexplore.ieee.org/document/8822143
  18. Simran Kharpude, Vaishnavi Hardikar, Gautam Munot, Omkar Lonkar and Vanita Agarwal, “ASL Recognition and Conversion to Speech”, in proceedings of Springer conference ICCNCT 2019, 23-24 May 2019, RVS Technical Campus, Coimbatore, Tamil Nadu, India. https://link.springer.com/chapter/10.1007/978-3-030-37051-0_53
  19. R. Patil and V. Agarwal, "Design of 128-Bit of Magnitude Comparator Using DPL Logic," 2017 International Conference on Computing, Communication, Control and Automation (ICCUBEA), 2017, pp. 1-5, doi: 10.1109/ICCUBEA.2017.8463922  

 

National Conferences

  1. Shankar Ambure, Vanita Agarwal, “Interface circuit design for capacitive sensing transducer in 0.18um CMOS technology”, IETE Cynosure, NCCEEE-2016, April 23-24, 2016, BATU, Lonere, India.
  2. Pravin Chingudi, Vanita Agarwal, “Standard Cell extraction scheme for improving timing model accuracy”, IETE Cynosure, NCCEEE-2016, April 23-24, 2016, BATU, Lonere, India.
  3. Jay P. Manvar, Bhavesh D. Radadiya, Vanita Agarwal, Mukul S. Sutaone, “A Novel Approach for False Minutiae Removal and Minutiae Based Fingerprint Matching”, 4th International Conference on Electronics Computer Technology (ICECT 2012), April 6 - 8, 2012, Kanyakumari, India.

 

Reviewer for Journals:

  • Mobile Network and Applications (MONET Journal for ACM-Springer) - 2017
  • IEEE IoT Journal - 2017, 2018
  • IEEE Systems Journal – 2019
  • Institute of Engineers, India (Series B) – 2020
  • SN Computer Science, Springer - 2023

 

M.Tech / B.Tech Students Guided:

No. of M.Tech Thesis guided since 2011 – 30+

No. of B.Tech Thesis guided since 2011 – 10+

 

Few UG Projects that can be viewed:

1. RST Stability Index and Accuracy Simulator

2. Python Libraries for Rough Set Theory

3. Performance Analysis of CNN Trained for Traffic Sign Recognition on Cadence Tensilica Processor

4. https://github.com/chinmaycodes7/sign-language-detection-two-way-communi...

Our Country needs research in many technical areas related to VLSI Domain. One of the most important being exploring Domain specific architecture for handling Inconsistent data.  Currently Working on Hardware design and development of Instruction Set design for Inconsistent Information System. It can help in developing Context Aware Concept generation for Cognitive Computing in Edge devices. 

Memberships and Affiliations: 

  • Senior Member  IEEE, Life Member IEI

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