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vsa.extc@coep.ac.in

Faculty

Designation: 

Assistant Professor

Email: 

vsa.extc@coep.ac.in

Mobile Number: 

9665366195

Phone Number: 

25507616

Teaching Experience: 

8

Research Experience: 

4

Qualifications: 

  • PhD, Pursuing
  • MTech, Microelectronics and VLSI Design, Indian Institute of Technology Bombay, India, 2010
  • B.E., Electronics & Telecommunication , Biju Pattnaik Technical University, Orissa, 2004

Workshops/FDP/Conferences/Lecture Series Organized:

  • TEQIP-II sponsored FDP on “Analog VLSI Design using Cadence tool”, December 10-14, 2014 by E&TC Department COEP and Entuple Technologies. Course Co-ordinators : Mrs Vaishali Ingale, Vanita Agarwal, Shatrughan Ransubhe.

  • Industry Academia relationship enhancement for VLSI under IET Pune chapter on 20th, 21st and 30th January 2012 for Post graduate students.

       Topics covered:

 

 

  • Power Semiconductor Devices by Fairchild Semiconductor India.
  •  Storage Technologies and Networking by LSI Pune.
  • Timing Analysis in Digital Circuits by NI2 Designs.

  • Functional verification techniques by LSI Pune.

  • Physical design flow by LSI Pune.

 

Research Interest:


  • Semiconductor Devices (Fabrication, Modeling and Characterization)
  • RTL Design and Verification
  • Processor Design
  • Artificial Intelligence
  • Hardware Security
  • Digital Circuit Design
  • Analog circuit design

Teaching Responsibility: 

  • Electron Devices and Circuits Theory and Lab (ET201 / ET205).
  • CMOS VLSI Design Theory and Lab (Post graduate students).
  • PLD & HDL and DSD & HDL Theory and Lab (Post graduate students).
  • RTL Simulation and Synthesis with PLDs Theory and Lab (Post graduate students).
  • ADCMOS Theory and Lab (Post graduate students).
  • PLD & Applications Theory and Lab (ET09013 / ET09017).
  • Digital CMOS Design Theory and Lab (Final yr. BTech).
  • Memory Technologies Theory and Lab (Post graduate students).
  • Network Analysis and Synthesis Lab and Integrated Circuits and Application Lab (ET207 / ET214).
  • Basic Electronics Engineering Theory and Lab (First year B.Tech).

Additional Responsibility: 

  • Lab In-charge for VLSI Design lab (2014 - date).
  • Faculty Advisor (2014 - date)
  • Postgraduate Syllabus design committee for VLSI and ES specialization - AICTE, COEP.
  • Departmental representative for NSS (National Social service).
  • Preparation of UGNBA and PGNBA SAR preparation committee member.
  • Departmental representative for AICTE report preparation committee member.
  • FE Admission duty.

Publications: 

  • Jay P. Manvar, Bhavesh D. Radadiya, Vanita Agarwal, Mukul S. Sutaone, “A Novel Approach for False Minutiae Removal and Minutiae Based Fingerprint Matching”,4th International Conference on Electronics Computer Technology (ICECT 2012), April 6 - 8, 2012, Kanyakumari, India.
  • Baldania Mukesh D, A. B. Patki, V. S. Agarwal, V. V. Ingale, “Verilog-HDL Based Implementation of a Fuzzy Logic Controller”, National conference on Information Theory and Communication Networks (NCITCN-2014), January 3-4, 2014, Pune, India.
  • Vanita Agarwal, Ashok Saraf, Dr R A Patil, "Design Security and Reconfigurable VLSI designs for strategic IP development", DEFCOM INDIA, Vol.2, No.1, Nov 2015, ISSN 2394-2398.
  • Nilesh S Khandekar, Vanita agarwal, " Timing closure and leakage optimization using MCMM optimization", ICEECMPE-PUNE, June 5, 2016, IE-EECMPEPUNE-05066-949, Pune, India.
  • Shankar Ambure, Vanita agarwal, "Interface circuit design for capacitive sensing transducer in 0.18um CMOS technology", IETE Cynosure, NCCEEE-2016, April 23-24, 2016, BATU, Lonere, India.
  • Pravin Chingudi, Vanita agarwal, "Standard Cell extraction scheme for improving timing model accuracy", IETE Cynosure, NCCEEE-2016, April 23-24, 2016, BATU, Lonere, India.
  • Reshma B Chougale, Vanita Agarwal, " Design of suitable Magnitude Comparator Architecture for Big Data Analytics", International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169, Volume: 5 Issue: 7.
  • Rashmi Patil, Vanita Agarwal, " Design of 128-bit of Magnitude Comparator Using DPL Logic", ICCUBEA 2017.
  • Ashish Jadhao, Vanita Agarwal, "Design of an Efficient Hardware Searching algorithm", International Research Journal of Engineering and Technology (IRJET), Volume: 05 Issue: 05, May 2018.
  • Vartul Sharma, Vanita Agarwal, "Design of Capacitor less LDO Regulator by using cascode compensation technique", International Research Journal of Engineering and Technology (IRJET), Volume: 05 Issue: 06, June 2018.
  • Sushil Shingade, Vanita Agarwal, " Design of Charge Pump for PLL with Reduction in Current Mismatch and Variation having Improved Voltage Swing", International Research Journal of Engineering and Technology (IRJET), Volume: 05 Issue: 06, June 2018.

Reviewer for Journals:


  • Mobile Network and Applications (MONET Journal for ACM-Springer) - 2017
  • IEEE IoT Journal - 2017, 2018
  • IEEE Systems Journal - 2019

M.Tech / B.Tech Students Guided:


M.Tech students guided

2011-12

  • Rohan Dileep Saravde - Implementing System-on-chip Physical design flow (Sponsored project).

  • Shankhapal Rajendra Balasaheb - Implementation of Linear Interpolation based 3-Axis CNC Machine motion controller in FPGA.

  • Ayush Ghosh - Electronic Power steering system (Sponsored project).

  • Jay Manvar - FPGA Implementation of Fingerprint Matching.

2013-14

  • Vishwajeet Kakde – Design of VCO and frequency divider using 90nm technology.

  • AjitSinh Chauhan - Diagnose Engine controller with Hardware in Loop (Sponsored project).

  • Rohit Bobade - Implementing 2 select arbiter using Parallel prefix architecture for DDR3.

2014-15

  • Snehal Kalaskar – Design of High Performance 64-points FFT Processor for MIMO OFDM systems.

  • Saurabh Jaipurkar – Design of Impedance Analyzer in 180 nm technology.

  • Sachin Thorbole – Design of PFD, Charge pump and LPF for higher frequency PLL in 90nm CMOS Technology.

2015-16

  • Mayur Katwe - FPGA based Remote I/O with MODBUS functionality.

  • Shankar Ambure - Interface circuit design for capacitive sensing in 0.18µm technology.

  • Pravin Chingudi - Standard cell extraction scheme for improving timing model accuracy (Sponsored project).

  • Nilesh S Khandekar - Timing closure and leakage power recovery using MCMM technique (Sponsored project).

2016 -17

  • Jyoti Adwani - Code Profiling for RST algorithm on DSP and Embedded Processors.

  • Reshma B Chougale - Design of suitable magnitude comparator architecture for Big Data analytics.

  • Rashmi Patil - Design of 128-bit of Magnitude comparator using DPL Logic.

  • Srikant Swami - Implementation of 16 bit Carry Look Ahead Adder in 90 nm Technology.

2017-18

  • Ashish Jadhao - Design of an Efficient Hardware Searching Algorithm.

  • Sushil Shingade - Design of Charge Pump for PLL with Reduction in Current Mismatch and Variation having Improved Voltage Swing

  • Akshay Thosar - Design of Relational Algebra ALU.

  • Vartul Sharma - Design of Capacitor less LDO Regulator by using cascode compensation technique

 

B.Tech students guided

  • Neha Bheniye, Vaishali Sahu, Priyanka Panchal, Priyanka Pawar - Graphene based FET device, 2010-2011.

  • Mandar A. Mande and Kunal M. Patel - Implementation of multi-protocol converter on FPGA , 2011-2012.

  • Churchill Khangar, Demendrakumar Bhagat, Vilas Shinde – Implementation of RS Codec on FPGA, 2013-14.

  • Suyash Uthale, Alka Kamble, Vishakha Dhotre – Convolution encoder and Viterbi decoder on FPGA, 2013-14.

  • Sayali S. Badambe, Deepika A. Telang, Rajani V. Chaniya - Wireless Sensor Network, 2015-16.

  • Shubhada Koli, Priyanka Tambe, Monica Gupta, Chandrika Nikam - Smart Wheelchair, 2016-17.

  • Omkar Tarawade, Nirali Shah, Raunak Jalori, Sheryl Santosh - Network Intrusion Detection System using Bloom filters, 2017-18.

 

International Journal (5)

  • · Vanita Agarwal, R. A. Patil, A. B. Patki, “Architectural Considerations for nest generation IoT Processors”, IEEE Systems Journal, Vol.13, No. 3, pp.2906 – 2917, September 2019.
  • · Vartul Sharma, Vanita Agarwal, "Design of Capacitor less LDO Regulator by using cascode compensation technique", International Research Journal of Engineering and Technology (IRJET), Volume: 05 Issue: 06, June 2018.
  • · Sushil Shingade, Vanita Agarwal, " Design of Charge Pump for PLL with Reduction in Current Mismatch and Variation having Improved Voltage Swing", International Research Journal of Engineering and Technology (IRJET), Volume: 05 Issue: 06, June 2018.
  • · Ashish Jadhao, Vanita Agarwal, "Design of an Efficient Hardware Searching algorithm",
  • International Research Journal of Engineering and Technology (IRJET), Volume: 05 Issue: 05, May 2018.
  • · Reshma B Chougale, Vanita Agarwal, " Design of suitable Magnitude Comparator Architecture for Big Data Analytics", International Journal on Recent and Innovation Trends in Computing and Communication ISSN: 2321-8169, Volume: 5 Issue: 7.

Memberships and Affiliations: 

  • Member of IEEE

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